Description
Menta provides two families of eFPGA augmented RISC microprocessors:
- Compact 32-bit microprocessor
- High-end 32-bit microprocessor, currently based on the © Gaisler Research LEON SPARC microprocessor family
Both solutions are based on standard 32-bit RISC microprocessor augmented with a proprietary ICS eFPGA core directly inserted into its instruction pipeline.
Target applications for these microprocessors based System-on-Chip (SoC) include digital signal processing, networking, telecommunication, wireless communication, security and multimedia.
These solutions lower the risks and NRE costs implied in ASIC development, while providing optimized system performance, low power consumption, and software programmability for bug fix / updates. This results in cost savings over the whole product lifetime. Additional benefits include reducing design task cycles since the same silicon may be re-used in multi-standard, multi-application product lines, allowing faster time-to-market.
MENTA IDE enables to take advantage of the reconfigurable hardware at C/C++ level, thanks to a complete suite of tools enabling to profile an application, extract the most computing intensive parts of it and translate them into hardware calls. Low-level access to the eFPGA configuration is nevertheless possible, thanks to a technology library which allows to make use of traditional logic synthesis tools for generating a set of configurations corresponding to the designer’ needs.
Compact microprocessor solutions
MENTA delivers ICS eFPGA augmented 32-bit RISC compact microprocessor. Due to small size of processor and with added flexibility of our eFPGA core which gives a performance boost the solution is very attractive for several applications. The prominent ones are DSP, networking and security/Cryptography. This solution provides an impressive performance boost at reduced cost.
Our solution supports the following features:
- 32-bit compact RISC microprocessor
- Pipelined hazard-free architecture
- Configurable MENTA ICS eFPGA core
- no MMU, Floating point units
- GCC Compiler support
- Preemptive multitasking kernel avaiable
- Optimized software libraries illustrating some algorithms mapped to the MENTA ICS eFPGA core
- MENTA specific tools: Profiling, Debugger, Place & Route, Simulator
High-end microprocessor solutions
The current MENTA ICS eFPGA has been implemented and validated into the proprietary © Gaisler Research LEON microprocessor family.
LEON microprocessor family features:
- 32-bit RISC processor
- SPARC V8 integer unit
- Hardware multiply, divide and MAC units
- Separate instruction and data cache
- Set-associative caches: 1 - 4 sets, 1 - 256 kbytes/set. Random, LRR or LRU replacement
- Data cache snooping
- AMBA-2.0 AHB and APB on-chip buses
- Power down mode.
- Multiprocessor-capable instruction set architecture (LEON3 only)
- Soft, Hard and Firm IP Cores available for rapid integration into SoC and ASIC
- Fully synthesizable, technology and fabrication independent using standard library and memory cells
- Operating system such as RTEMS, µCLinux and eCos are available
- Industry standard GNU software development tools available for both Windows and UNIX enviroments
Additional features brought by MENTA:
- configurable MENTA ICS eFPGA core
- Optimized software libraries illustrating some algorithms mapped to the MENTA ICS eFPGA core
- MENTA Kernel module for Operating System
- MENTA specific tools: Profiling, Debugger, Place & Route, Simulator.
For these solutions a specific licensing procedure with both MENTA and GAISLER Research is needed, contact us for more information on that.